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User Guide
COMe-bP5020
3.3 I/O Address Map
For the COMe-bP5020, the register address is composed of the base address of the Onboard Logic indicated in the virtual mem-
ory map (see Table 14) and the respective address offset indicated in the I/O address map (Table 15):
register address = 0xFF00_0000 base + address offset.
Table 15: I/O Address Map
ADDRESS OFFSET DEVICE ACRONYM
0x003 GPIO Direction Register 0 GPDIR0
0x004 GPIO Direction Register 1 GPDIR1
0x005 GPIO Data Register 0 GPDAT0
0x006 GPIO Data Register 1 GPDAT1
0x280 Status Register 0 STAT0
0x284 Device Protection Register DPROT
0x285 Reset Status Register RSTAT
0x288 Board ID High Byte Register BIDH
0x289 Board and PLD Revision Register BREV
0x28C Watchdog Timer Control Register WTIM
0x28D Board ID Low Byte Register BIDL
0x374 Carrier Interrupt Mode 1 CIM1
0x375 Carrier Interrupt Mode 2 CIM2
0x376 Board Interrupt Pending Register 1 BIPR1
0x377 Board Interrupt Pending Register 2 BIPR2
0x378 Board Interrupt Pending Register 3 BIPR3
0x37A Board Interrupt Enable 1 BIE1
0x37B Board Interrupt Enable 2 BIE2
0x380 Interrupt Multiplexer 1 Register IMUX1
0x381 Interrupt Multiplexer 2 Register IMUX2
0x390 Carrier Control Register CCR
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