Kontron COMe-bHL6 Bedienungsanleitung Seite 90
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COMe-bHL6 / BIOS Operation
Watchdog
Feature Options Description
Auto-reload
Disabled
Enabled
Enable automatic reload of watchdog timers on timeout
Global Lock
Disabled
Enabled
If set to enabled, all Watchdog registers (except
WD_KICK) become read only until the board is reset
Stage 1 Mode
Disabled
Reset
NMI
SCI
Select Action for first Watchdog stage
- Assert WDT Signal
Enabled
Disabled
Enable/Disable assertion of WDT signal to baseboard on
stage timeout
- Stage 1 Timeout 1s
5s
10s
30s
1m
3m
10m
30m
Select Timeout value for first watchdog stage
Stage 2 Mode
Disabled
Reset
NMI
SCI
Select Action for first Watchdog stage
- Assert WDT Signal
Disabled
Enabled
Enable/Disable assertion of WDT signal to baseboard on
stage timeout
- Stage 2 Timeout 1s
5s
10s
30s
1m
3m
10m
30m
Select Timeout value for second watchdog stage
90
- COMe-bHL6 1
- » Table of Contents « 3
- 1 User Information 6
- 1.5 Warranty 7
- 1.6 Technical Support 7
- 2 Introduction 8
- COMe-bHL6 / Introduction 9
- 2.5 COM Express® Benefits 10
- 3 Product Specification 11
- 3.2 Functional Specification 12
- CPU Features 14
- PCH comparison 16
- Graphics Core 17
- PEG Configuration 18
- Connectivity 19
- Misc Interfaces and Features 19
- Kontron Features 20
- Additional features 20
- Power Features 20
- 3.3 Block Diagram 21
- 3.4 Accessories 22
- 3.5 Electrical Specification 23
- 3.5.5 ATX Mode 24
- 3.5.6 Single Supply Mode 24
- 3.6 Power Control 25
- 3.7.2 Humidity 26
- WEEE Directive 27
- Conformal Coating 27
- Shock & Vibration 28
- 3.9 MTBF 29
- 3.10 Mechanical Specification 30
- 3.11 Module Dimensions 31
- 3.13 Onboard Connectors 33
- 4 Features and Interfaces 35
- 4.2 Rapid Shutdown 36
- 4.5 SPI boot 39
- Using an external SPI flash 40
- 4.6 M.A.R.S 41
- 4.7 UART 42
- 4.8 Fast I2C 43
- Time-out events 44
- WDT Signal 44
- 4.11 Speedstep Technology 47
- 4.12 C-States 48
- 4.13 Hyper Threading 49
- 4.15 VID-x 51
- 4.17 Display Configuration 53
- 3 independent Display Support 54
- DDI Design Consideration 55
- DVI-I Design Topology 55
- Requirements 56
- Setup a Multi-monitor system 56
- 4.19 Intel® Wireless Display 57
- 4.20 Intel® vPro™ technology 59
- 5 System Resources 61
- 5.2 Memory Area 62
- 5.3 I/O Address Map 62
- 5.5 Internal I2C Bus 63
- 5.6 External I2C Bus 63
- 6 Connectors 65
- 7 Pinout List 66
- 7.2 Connector X1A Row A 67
- COMe-bHL6 / Pinout List 68
- 7.3 Connector X1A Row B 69
- 7.4 Connector X1B Row C 71
- 7.5 Connector X1B Row D 73
- 8 BIOS Operation 75
- 8.5 BIOS Setup 76
- System Information 78
- Boot Features 79
- Network Stack 81
- Platform Information 82
- 8.5.2 Advanced 83
- Silicon Information 84
- Processor Configuration 85
- Processor Power Management 86
- Miscellaneous 88
- I2C Speed 89
- Watchdog 90
- Generic LPC Decode Ranges 91
- H/W Monitor 92
- HDD Configuration 94
- Memory Configuration 96
- Graphics Configuration 99
- COMe-bHL6 / BIOS Operation 100
- IGD Configuration 101
- PEG Port Configuration 103
- South Bridge Configuration 105
- SB PCI Express Config 106
- SB USB Config 108
- SB Azalia Config 109
- Network Configuration 110
- CPLD Configuration 111
- LPC SIO Configuration 112
- ME Configuration (default) 115
- Thermal Configuration 117
- CPU Thermal Configuration 118
- Passive Cooling 120
- ICC Configuration 121
- Intel® Rapid Start Technology 123
- 8.5.3 Security 125
- Security 126
- 8.5.4 Boot 127
- 8.5.5 Exit 128
- Corporate Offices 129
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