Kontron COMe Starterkit Eval T2 Bedienungsanleitung

COM Express®Carrier Design GuideGuidelines for designing COM Express® Carrier BoardsDecember 6, 2013Rev. 2.0This design guide is not a specification.

Preface1.7. Intellectual propertyThe Consortium draws attention to the fact that implementing recommendations made in this document could involve the

COM Express Interfaces2.12.2. Reference SchematicsFigure 35: eDP Reference SchematicThe reference schematic provides a generic eDP interface. The eD

COM Express Interfaces2.13. VGA2.13.1. Signal DefinitionsThe COM Express Specification defines an analog VGA RGB interface for all Module types, exc

COM Express Interfaces2.13.3. VGA Reference SchematicsThis reference schematic shows a circuitry implementing a VGA port.Figure 37: VGA Reference Sch

COM Express Interfaces2.13.4. Routing Considerations2.13.4.1. RGB Analog SignalsThe RGB signal interface of the COM Express Module consists of three

COM Express Interfaces2.14. TV-OutTV-Out signals have been removed in COM.0 Rev. 2.0 and the former content of this chapter canstill be found in the

COM Express Interfaces2.15. Digital Audio InterfacesThe COM Express Specification allocates seven pins on the A-B connector to support digital AC’97

COM Express InterfacesFigure 38: Multiple Audio Codec ConfigurationPICMG® COM Express® Carrier Board Design Guide Rev. 2.0 / December 6, 2013106/218CO

COM Express Interfaces2.15.1. Reference Schematics2.15.1.1. High Definition AudioFigure 39: HDA Example SchematicPICMG® COM Express® Carrier Board D

COM Express Interfaces2.15.1.2. AC'97Figure 40: AC'97 Schematic ExamplePICMG® COM Express® Carrier Board Design Guide Draft Rev. 2.0 / Dece

COM Express InterfacesFigure 41: Audio AmplifierThe example above shows a traditional class AB amplifier. There are many physically smaller and more

Preface1.8. Acronyms, Abbreviations and Definitions UsedTable 1: Acronyms, Abbreviations and Definitions UsedTerm DescriptionAC ‘97 / HDA Audio CODEC

COM Express Interfaces2.15.1.3. Routing ConsiderationsThe implementation of proper component placement and routing techniques will help to ensure tha

COM Express Interfaces2.16. LPC Bus – Low Pin Count InterfaceSince COM Express is designed to be a legacy free standard for embedded Modules, it does

COM Express InterfacesCarrier designers should not buffer LPC_CLK for maximum Module interoperability. The COM Express specification intends for a si

COM Express Interfaces2.16.2.3. LPC PLD Example – Port 80 DecoderFigure 43: LPC PLD Example – Port 80 Decoder SchematicPICMG® COM Express® Carrier Bo

COM Express InterfacesThe following applies to Figure 43 above.The JTAG header may be used to program the PLD in-circuit.The LPC bus is the interface

COM Express Interfaces2.16.2.4. SuperIOFigure 44: LPC Super I/O ExamplePICMG® COM Express® Carrier Board Design Guide Rev. 2.0 / December 6, 2013115/

COM Express InterfacesFigure 45: LPC Serial InterfacesNote: Connection between logic GND and chassis depends on grounding architecture. Connect GND w

COM Express InterfacesThe LPC clock implementation should follow the routing guidelines for the PCI clock defined in the COM Express specification and

COM Express Interfaces2.17. SPI – Serial Peripheral Interface BusThe SPI interface is defined in this specification to service as an off-module optio

COM Express InterfacesTable 36: Effect of the BIOS disable signalsBIOS_DIS1# BIOS_DIS0# Chipset SPI CS1# DestinationChipset SPI CS0# DestinationCarrie

PrefaceTerm DescriptionHDMI High Definition Multimedia InterfaceI2C Inter Integrated Circuit – 2 wire (clock and data) signaling scheme allowing commu

COM Express InterfacesThe optional connector J32 offers the possibility to program the flash device with an external programmer.The flash device can b

COM Express Interfaces2.18. General Purpose I2C Bus InterfaceThe I2C (Inter-Integrated Circuit) bus is a two-wire serial bus originally defined by Ph

COM Express InterfacesSpecification. The circuitry in Figure 47 below shows how to connect an Atmel 'AT24C04' 4kbit EEPROM to the General P

COM Express Interfaces2.19. System Management Bus (SMBus)The SMBus is primarily used as an interface to manage peripherals such as serial presence de

COM Express Interfaces2.19.2. Routing ConsiderationsThe SMBus should be connected to all or none of the PCIe/PCI devices and slots. A general recomm

COM Express Interfaces2.20. General Purpose Serial InterfaceSince Revision 2.0 of the COM Express specification two optional serial ports are availab

COM Express Interfaces2.20.2. Reference Schematics2.20.2.1. General Purpose Serial Port ExampleFigure 49: General Purpose Serial Port Example Figure

COM Express Interfaces2.21. CAN InterfaceCAN bus is a vehicle bus standard designed to allow controllers and devices to communicate with each other w

COM Express Interfaces2.21.2. Reference Schematics2.21.2.1. CAN Bus ExampleFigure 50: CAN Bus ExampleFigure 50: CAN Bus Example shows the schematics

COM Express Interfaces2.22. Miscellaneous SignalsTable 42: Miscellaneous SignalsSignal Pin Description I/O CommentTYPE0#TYPE1#TYPE2#C54C57D57The Type

PrefaceTerm DescriptionSMBus System Management BusSO-DIMM Small Outline Dual In-line Memory ModuleSPI Serial Peripheral InterfaceTBD To be determinedT

COM Express Interfaces2.22.1. Module Type DetectionThe COM Express Specification includes three signals to determine the pin-out type of the Module c

COM Express InterfacesFigure 51: Module Type 2 Detection CircuitryPICMG® COM Express® Carrier Board Design Guide Rev. 2.0 / December 6, 2013131/218

COM Express InterfacesPICMG® COM Express® Carrier Board Design Guide Rev. 2.0 / December 6, 2013132/218

COM Express Interfaces2.22.2. Speaker OutputThe PC-AT architecture provides a speaker signal that creates beeps and chirps. The signal is a digital-

COM Express Interfaces2.22.3. RTC Battery ImplementationThe Real Time Clock (RTC) is responsible for maintaining the time and date even when the COME

COM Express Interfaces2.22.4. Power Management SignalsCOM Express specifies a set of signals to control the system power states such as the power-on

COM Express InterfacesSignal Pin Description I/O CommentSUS_S5# A24 S5 Sleep Control signal indicating that the system resides in S5 State (Soft Off).

COM Express Interfaces2.22.5. Watchdog TimerFigure 54: Watchdog Timer Event Latch SchematicThe Watchdog Timer (WDT) event signal is provided by the C

COM Express Interfaces2.22.6. General Purpose Input/Output (GPIO)Table 46: GPIO Signal DefinitionSignal Pin Description I/O CommentGPI0 A54 General p

COM Express InterfacesFigure 55: General Purpose I/O Loop-back SchematicThere are 4 GPI (General Purpose Inputs) and 4 GPO (General Purpose Outputs) p

Preface1.9. Signal Table TerminologyTable 2 below describes the terminology used in this section for the Signal Description tables. The “#” symbol a

COM Express Interfaces2.22.7. SDIO Interface Multiplexed with GPIOsSD Card support was added in COM.0 Rev. 2.0 as an alternative use for the GPIO pin

COM Express InterfacesFigure 56: SDIO Interface Multiplexed with GPIOsPICMG® COM Express® Carrier Board Design Guide Draft Rev. 2.0 / December 6, 2013

COM Express Interfaces2.22.8. Fan ConnectorFigure 57: Fan Connector Reference SchematicFAN_TACHIN and FAN_PWMOUT in Figure 57: Fan Connector Referenc

COM Express Interfaces2.22.9. Thermal InterfaceCOM Express provides the 'THRM#' and 'THRMTRIP#' signals, which are used for syst

COM Express Interfaces2.22.10. Protecting COM.0 Pins Reclaimed From the VCC_12V PoolThe COM.0 Rev. 2 Type 6 and Type 10 pin-out types introduce eight

COM Express InterfacesFigure 58: Protecting Logic Level Signals on Pins Reclaimed from VCC_12VPICMG® COM Express® Carrier Board Design Guide Rev. 2.0

COM Express Interfaces2.22.10.2. TYPE10# Strap - Reclaimed from VCC_12VNo additional protection is needed for the TYPE10# strap on the Module side:

COM Express Interfaces2.23. PCI Bus2.23.1. Signal DefinitionsType 2 and 3 COM Express Modules provide a 32-bit PCI bus that can operate up to 33 MHz

COM Express InterfacesSignal Pin# Description I/O CommentPCI_STOP# D34 PCI bus STOP control line, active low I/O 3.3VPCI_PAR D32 PCI bus parity I/O 3.

COM Express InterfacesFigure 59: PCI Bus Interrupt RoutingMost of these PCI devices only utilize the interrupt signal 'INTA#'. To distribut

Preface1.10. Schematic ConventionsSchematic examples are drawn with signal directions shown per the figure below. Signals that connect directly to t

COM Express Interfaces2.23.2.2. Device-Down ExampleFigure 60: PCI Device Down Example; Dual UARTPICMG® COM Express® Carrier Board Design Guide Draft

COM Express Interfaces2.23.2.3. Device-Down Considerations2.23.2.4. Clock BufferThe COM Express Specification only supports a single PCI clock signa

COM Express InterfacesThe clock trace from the COM Express Module to a PCI bus slot should be 2.5 inches shorter because PCI cards are specified to ha

COM Express Interfaces2.24. IDE and CompactFlash (PATA)2.24.1. Signal DefinitionsType 2 and 4 COM Express Modules provide a single channel IDE inter

COM Express InterfacesSignal Pin Description I/O IDE40 IDE44 CFCSEL 28 28 39N.C. 20, 32 20, 32, 44 24, 40, 51, 52, 53, 54, 55, 5639 (slave)VCC_5V 41,

COM Express InterfacesFigure 63: IDE 40 Pin and CompactFlash 50 Pin Connector2.24.6. Routing ConsiderationsThe IDE signals are single-ended signals w

Power and Reset3. Power and Reset3.1. General Power requirementsCOM Express calls for the Module to be powered by a single 12V power rail, with a +/

Power and Reset3.2. ATX and AT Style Power Control3.2.1. ATX vs AT SuppliesATX power supplies are in common use in contemporary PCs. ATX supplies h

Power and Reset3.2.3. ATX and AT Power Sequencing DiagramsA sequence diagram for an ATX style boot from a soft-off state (S5), initiated by a power b

Power and ResetFigure 64: ATX Style Boot – Controlled by Power ButtonPICMG® COM Express® Carrier Board Design Guide Draft Rev. 2.0 / December 6, 2013

COM Express Interfaces2. COM Express InterfacesThe following section summarizes the signals found on COM Express Type 10, Type 2 and Type 6 connector

Power and ResetFigure 65: AT Style Power Up BootTable 53 below indicates roughly what time ranges can be expected during the boot process, per Figure

Power and ResetTable 53: ATX and AT Power Up Timing ValuesParameter Min ValueMax ValueDescription CommentsTPB 10ms 500ms Push Button Power Switch – ti

Power and Reset3.2.5. Power ButtonThe COM Express PWRBTN# input may be used by Carrier Board hardware to implement ATX style power control. A schema

Power and Reset3.3. Design Considerations for Carrier Boards containing FPGAs/CPLDsVery often, the Carrier Board will contain custom FPGA or other pr

Power and Reset3.4. Reference Schematics3.4.1. ATX Power SupplyATX power supplies are used in millions of desktop PCs and are often used in OEM equi

Power and ResetFigure 66: AT and ATX Power SupplyPICMG® COM Express® Carrier Board Design Guide Draft Rev. 2.0 / December 6, 2013 165/218

Power and ResetThe PWRBTN# signal is an input to the COM Express Module. Switch de-bouncing is done on the Module. The falling edge of the PWRBTN# s

Power and Reset3.5. Routing Considerations3.5.1. VCC_12V and GNDThe primary consideration for the +12V power input (VCC_12V) to the Module is that t

Power and ResetTable 56: Approximate Copper Trace Current Capability per IPC-2221 ChartsTrace Type Max Current with 10°C Temp Rise Max Current with 20

Power and Reset3.5.5. Slot Card Supply Decoupling RecommendationsImplementing PCI Express connectors on the Carrier Board requires decoupling of the

COM Express InterfacesFigure 2: COM Express Type 10 Connector LayoutPICMG® COM Express® Carrier Board Design Guide Rev. 2.0 / December 6, 201317/218C

BIOS Considerations4. BIOS Considerations4.1. Legacy versus Legacy-FreeFor the purposes of this document, “legacy” refers to a set of peripherals pr

COM Express Module Connectors5. COM Express Module Connectors5.1. Connector DescriptionsA pair of 220-pin COM Express Carrier-Board connectors is av

COM Express Module Connectorspeg location holes in the PCB connector pattern are in the correct positions (as shown in the landpattern of the COM Expr

Carrier Board PCB Layout Guidelines6. Carrier Board PCB Layout Guidelines6.1. General6.2. PCB Stack-upsNote Section 6 'Carrier Board PCB Layou

Carrier Board PCB Layout GuidelinesFigure 69 above is an example of a six layer stack-up. Layers L1, L3, L4 and L6 are used for signal-routing. Laye

Carrier Board PCB Layout Guidelines6.3. Trace-Impedance ConsiderationsMost high-speed interfaces used in an COM Express design for a Carrier Board ar

Carrier Board PCB Layout GuidelinesFigure 71: Microstrip Cross SectionFigure 72: Strip Line Cross SectionTable 60: Trace ParametersSymbol Definitionεr

Carrier Board PCB Layout Guidelines6.4. Trace-Length Extensions ConsiderationsHigh speed differential signals need controlled impedance and according

Carrier Board PCB Layout Guidelines6.5. Routing Rules for High-Speed Differential InterfacesThe following is a list of suggestions for designing with

Carrier Board PCB Layout GuidelinesFigure 74: Layout ConsiderationsPICMG® COM Express® Carrier Board Design Guide Rev. 2.0 / December 6, 2013179/218

COM Express InterfacesFigure 3: COM Express Type 2 Connector LayoutPICMG® COM Express® Carrier Board Design Guide Rev. 2.0 / December 6, 201318/218PAT

Carrier Board PCB Layout GuidelinesPICMG® COM Express® Carrier Board Design Guide Rev. 2.0 / December 6, 2013180/218

Carrier Board PCB Layout GuidelinesIn order to determine the necessary trace width, trace height and spacing needed to fulfill the requirements of the

Carrier Board PCB Layout Guidelines6.5.1. PCI Express Trace Routing GuidelinesTable 61: PCI Express Trace Routing GuidelinesParameter PCIe Gen1 PCIe

Carrier Board PCB Layout Guidelines6.5.2. USB Trace Routing GuidelinesTable 62: USB Trace Routing GuidelinesParameter Trace RoutingTransfer rate / Po

Carrier Board PCB Layout Guidelines6.5.3. USB 3.0 Trace Routing GuidelinesTable 63: USB 3.0 Trace Routing GuidelinesParameter Trace RoutingTransfer r

Carrier Board PCB Layout Guidelines6.5.5. SDVO Trace Routing GuidelinesTable 64: SDVO Trace Routing GuidelinesParameter Trace RoutingTransfer Rate /

Carrier Board PCB Layout Guidelines6.5.6. DisplayPort Trace Routing GuidelinesTable 65: DisplayPort Trace Routing GuidelinesParameter Trace RoutingTr

Carrier Board PCB Layout Guidelines6.5.7. LAN Trace Routing GuidelinesTable 66: LAN Trace Routing GuidelinesParameter Trace RoutingSignal length allo

Carrier Board PCB Layout Guidelines6.5.8. Serial ATA Trace Routing GuidelinesTable 67: Serial ATA Trace Routing GuidelinesParameter Trace RoutingTran

Carrier Board PCB Layout Guidelines6.5.9. LVDS Trace Routing GuidelinesTable 68: LVDS Trace Routing GuidelinesParameter Trace RoutingMaximum signal l

COM Express InterfacesFigure 4: COM Express Type 6 Connector LayoutPICMG® COM Express® Carrier Board Design Guide Rev. 2.0 / December 6, 201319/218M o

Carrier Board PCB Layout Guidelines6.6. Routing Rules for Single Ended InterfacesThe following is a list of suggestions for designing with single end

Carrier Board PCB Layout Guidelines6.6.1. PCI Trace Routing GuidelinesTable 69: PCI Trace Routing GuidelinesParameter Trace RoutingTransfer Rate @ 33

Carrier Board PCB Layout Guidelines6.6.2. IDE Trace Routing GuidelinesTable 70: IDE Trace Routing GuidelinesParameter Trace RoutingMaximum Transfer R

Carrier Board PCB Layout Guidelines6.6.3. LPC Trace Routing GuidelinesTable 71: LPC Trace Routing GuidelinesParameter Trace RoutingTransfer Rate @ 33

Mechanical Considerations7. Mechanical Considerations7.1. Form FactorsThe COM Express specification describes 4 different sized COM Express Modules.

Mechanical Considerations7.2. HeatspreaderAn important factor for each system integration is the thermal design. The heatspreader acts as a thermal

Mechanical Considerations7.2.1. Top mountingFor top mounting heatspreaders with non-threaded standoffs (bore hole) are used.This variant of the heats

Mechanical Considerations7.2.2. Bottom mountingHeatspreaders with threaded standoffs are used for bottom-mounting solutions.This variant of the heats

Mechanical ConsiderationsTable 72: Heatspreader mounting material needed (5mm connectors at the Carrier Board)Component Quantity CommentM2.5 x 16mm sc

Applicable Documents and Standards8. Applicable Documents and Standards8.1. Technology SpecificationsTable 75: Reference specificationsSpecification

© Copyright 2013, PCI Industrial Computer Manufacturers Group. The attention of adopters is directed to the possibility that compliance with or adopt

COM Express Interfaces2.1.1. Connector Pin-out ComparisonTable 4: Pin-out ComparisonPin# Type 10 Description Type 2 Description Type 6 DescriptionA1

Applicable Documents and StandardsSpecification Description LinkPCI Express Mobile Graphics Low-Power Addendum to the PCI Express Base Specificationww

Applicable Documents and Standards8.2. Regulatory SpecificationsFCC Rules Part 15 Class B devicesEN 61000-4-2 Personnel Electrostatic Discharge Immun

Applicable Documents and Standards8.3. Useful booksTable 76: Useful booksTitle Author NotePCI Express System Architecture Ravi Budruk, Don Anderson,

Appendix A: Deprecated Features9. Appendix A: Deprecated FeaturesThe following content was removed from the main part of this document because it is

Appendix A: Deprecated FeaturesTable 78: TV-Out Connector Pin-outPin Signal Description Pin Signal Description1 Chrominance (C) S-Video Chrominance An

Appendix A: Deprecated Features9.1.3. TV-Out Reference SchematicsAll signals along the left edge of the figure below are sourced directly from the CO

Appendix A: Deprecated Features9.1.4. Routing ConsiderationsAt least 30mils of spacing should be used for the routing between each TV-DAC channel to

Appendix A: Deprecated Features9.2. LPC Firmware HubAn example of a Carrier Board Firmware Hub (FWH) implementation is shown in Figure 80: LPC Firmwa

Appendix A: Deprecated FeaturesThe BIOS device shown in Figure 80: LPC Firmware Hub above is a SST SST49LF008A Firmware Hub in a 32-pin PLCC package.

Appendix B: Sourcecode for Port 80 Decoder10. Appendix B: Sourcecode for Port 80 Decoder-- IO80 catcher for LPC bus.-- File: LPC_IOW80_1.1.VHD-- Rev

COM Express InterfacesPin# Type 10 Description Type 2 Description Type 6 DescriptionA44 USB_2_3_OC# USB_2_3_OC# USB_2_3_OC# A45 USB0- USB0-

Appendix B: Sourcecode for Port 80 Decoder----------------------------------------------------------------------------- LPC state machine-- LPC_State

Appendix B: Sourcecode for Port 80 DecoderLPC_State <= IDLE; -- abort cycle, bad frame -- or address mismatchelse-- Write address valid. Subseq

Appendix B: Sourcecode for Port 80 Decoderwhen "0111" => seven_seg_H <= "00011111"; -- Hex 1f displays a 7when "1000&

Appendix C: List of Tables11. Appendix C: List of TablesTable 1: Acronyms, Abbreviations and Definitions Used...

Appendix C: List of TablesTable 45: Power Management Signal Descriptions...

Appendix D: List of Figures12. Appendix D: List of FiguresFigure 1: Schematic Conventions...

Appendix D: List of FiguresFigure 48: System Management Bus Separation...

Appendix E: Revision History13. Appendix E: Revision HistoryTable 79: Revision HistoryRevision Date Author Changes1.00 RC1.0 Jan 16, 2009 C. Eder1.10

Appendix E: Revision HistoryAdded Note for later updated PCI Gen 3.0 Layout Rules2.0 beta 0.7 April, 9, 2013 M. Unverdorben Implementation of COM_CRs_

COM Express InterfacesPin# Type 10 Description Type 2 Description Type 6 DescriptionA90 GND(FIXED) GND(FIXED) GND(FIXED) A91 SPI_POWER SPI

COM Express InterfacesPin# Type 10 Description Type 2 Description Type 6 DescriptionB26 USB_SSTX1+ SATA3_RX- SATA3_RX- B27 WDT WDT WDT B

COM Express InterfacesPin# Type 10 Description Type 2 Description Type 6 DescriptionB72 DDI0_PAIR0- LVDS_B0- LVDS_B0- B73 DDI0_PAIR1+ LVDS_B1

COM Express InterfacesPin# Type 10 Description Type 2 Description Type 6 DescriptionC8 - IDE_D2 GND C9 - IDE_D13 USB_SSRX2- C10 - IDE_D1

COM Express InterfacesPin# Type 10 Description Type 2 Description Type 6 DescriptionC54 - TYPE0# TYPE0# C55 - PEG_RX1+ PEG_RX1+ C56 - PEG_R

COM Express InterfacesPin# Type 10 Description Type 2 Description Type 6 DescriptionC100 - GND(FIXED) GND(FIXED) C101 - PEG_RX15+ PEG_RX15+

COM Express InterfacesPin# Type 10 Description Type 2 Description Type 6 DescriptionD36 - PCI_FRAME# DDI1_PAIR3+ D37 - PCI_AD16 DDI1_PAIR3- D

COM Express InterfacesPin# Type 10 Description Type 2 Description Type 6 DescriptionD82 - PEG_TX9- PEG_TX9- D83 - RSVD RSVDD84 - GND GND D85

Contents1. Preface...8

COM Express Interfaces2.2. PCIe General IntroductionPCI Express provides a scalable, high-speed, serial I/O point-to-point bus connection. A PCI Exp

COM Express Interfaces2.3. General Purpose PCIe Lanes2.3.1. General Purpose PCIe Signal DefinitionsThe general purpose PCI Express interface of the

COM Express InterfacesSignal Pin# Description I/O CommentSYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum spec

COM Express Interfaces2.3.4. Device Up / Device Down and PCIe Rx / Tx Coupling CapacitorsFigure 5: PCIe Rx Coupling Capacitors“Device Down” refers to

COM Express Interfaces2.3.5. Schematic Examples2.3.5.1. Reference Clock BufferThe COM Express Specification calls for one copy of the PCIe reference

COM Express InterfacesFigure 6: PCIe Reference Clock BufferThe following notes apply to Figure 6 'PCIe Reference Clock Buffer'.Nets that tie

COM Express InterfacesEach clock output pair in the example shown is terminated close to the IDT9DB433 buffer pins with a series resistor (shown as 33

COM Express Interfaces2.3.5.2. ResetThe PCI Interface of the COM Express Type 2 Module shares the reset signal 'PCI_RESET#' with the PCI Ex

COM Express Interfacespin will be read high. Software then uses this information to apply power to the card. There is nostandard input port pin defi

COM Express Interfaces2.3.5.5. PCIe x1 Generic Device Down ExampleFigure 9: PCI Express x1 Generic Device Down ExampleA generic example of a PCIe x1

2.8.4. Routing Considerations...802.9. USB 3.0...

COM Express Interfaces2.3.5.6. PCIe x4 Generic Device Down ExampleFigure 10: PCI Express x4 Generic Device Down ExampleA generic example of a PCIe x4

COM Express InterfacesPCI Express Mini Cards are popular for implementing features such as wireless LAN. A small footprint connector can be implement

COM Express InterfacesFigure 13: PCI Express Mini Card Connector on COM Express Carrier BoardThe different card sized can be easily handled on the Car

COM Express InterfacesTable 7: PCIe Mini Card Connector Pin-outPin Signal Description Pin Signal Description1 WAKE# Requests the host interface to ret

COM Express InterfacesFigure 14: PCIe Mini Card Reference CircuitryA PCI Express Mini Card schematic example is shown in Figure 14 above. The referen

COM Express InterfacesTable 8: Support Signals for ExpressCardSignal Pin Description I/OEXCD0_CPPE# A49 ExpressCard capable card request, slot 0. I 3.

COM Express InterfacesFigure 17: PCI Express: ExpressCard ExampleFigure 17 above shows an ExpressCard implementation. The example shows COM Express P

COM Express InterfacesThe TPS2231 includes a number of integrated pull-up resistors. Other solutions may require external pull-ups not shown in this

COM Express Interfaces2.4. PEG (PCI Express Graphics)2.4.1. Signal DefinitionsThe PEG Port can utilize COM Express PCIe lanes 16-31 and is suitable

COM Express InterfacesSignal Pin# Description I/O CommentPEG_TX9+PEG_TX9-D81D82PEG channel 9, Transmit Output differential pair.O PCIEPEG_RX10+PEG_RX1

2.21.1. Signal Definitions...1272.21.2. Refe

COM Express Interfaces2.4.2.1. Using PEG Pins for an External Graphics CardTo use the COM Express PEG lanes for an external graphics device or card,

COM Express InterfacesModules that employ desktop and mobile chip-sets with PEG capability can usually be set up to allow the COM Express PEG lanes to

COM Express Interfaces2.4.3. Reference Schematics2.4.3.1. x1, x4, x8, x16 SlotFigure 18 below illustrates the pin-out definition for the standard x1

COM Express InterfacesThe x16 connector usually is used to drive the PCI Express Graphics Port (PEG) consisting of 16PEG lanes, which are connected to

COM Express InterfacesFigure 19: PEG Lane Reversal ModeTo activate the Lane Reversal mode for the PEG Port, the COM Express specification defines an a

COM Express Interfaces2.5. Digital Display InterfacesModule Types 6 and 10 use Digital Display Interfaces (DDI) to provide DisplayPort, HDMI/DVI, and

COM Express Interfaces2.5.1.2. Reference SchematicDisplayPort ExampleFigure 20: DisplayPort Reference SchematicsDisplayPort is directly supported by

COM Express InterfacesHDMI ExampleFigure 21: HDMI ExamplePICMG® COM Express® Carrier Board Design Guide Draft Rev. 2.0 / December 6, 2013 57/218use wi

COM Express InterfacesA Dual-mode source Module requires level shifters on the Carrier to convert the low-swing AC coupled differential pairs from the

COM Express InterfacesDVI ExampleFigure 22: DVI ExamplePICMG® COM Express® Carrier Board Design Guide Draft Rev. 2.0 / December 6, 2013 59/218SHIELD_G

4.2. Super I/O... 1685. COM

COM Express InterfacesA Dual-mode source Module requires level shifters on the Carrier to convert the low-swing AC coupled differential pairs from the

COM Express Interfaces2.5.2. SDVOSDVO was developed by the Intel® Corporation to interface third party SDVO compliant display controller devices that

COM Express InterfacesSupported SDVO DevicesDue to the fact that SDVO is an Intel® defined interface, the number of supported SDVO devices is limited

COM Express Interfaces2.5.2.2. Reference SchematicsSDVO to DVI Transmitter ExampleFigure 23: SDVO to DVI Transmitter ExampleFigure 23 'SDVO to D

COM Express InterfacesPEG_RX1+ and PEG_RX1- are sourced from COM Express Module pins C55 and C56 and are defined as SDVOB_INT+ and SDVOB_INT- in the C

COM Express InterfacesThe Digital Video Interface (DVI) is based on the differential signaling method TDMS. To achievethe full performance and reliab

COM Express Interfaces2.6. Mobile PCI Express Module (MXM)Mobile PCI Express Module is an interconnect standard for GPUs defined by the MXM-SIG, main

COM Express InterfacesThe MXM3 Module shown in this example supports two DisplayPort channels. They are designated DP1 and DP3 on the schematic. The

COM Express Interfaces2.6.2. Reference SchematicsFigure 24: MXM Reference SchematicsPICMG® COM Express® Carrier Board Design Guide Draft Rev. 2.0 / D

COM Express InterfacesFigure 25: DisplayPort implementation of MXM interface (one channel)Following notes apply to Figure 24: MXM Reference Schematics

9.1.4. Routing Considerations...2029.1.5. Signal Termi

COM Express Interfaces2.7. LANAll COM Express Modules provide at least one LAN port. The 8-wire 10/100/1000BASE-T Gigabit Ethernet interface complia

COM Express InterfacesTable 17: LAN Interface LED FunctionLED-Function LED Color# LED State DescriptionLink Speed Green / Orange Off 10 Mbps link spee

COM Express InterfacesAs there are a large number of Ethernet PHY components and coupling transformers on the market, it is strongly recommended that

COM Express Interfaces2.7.2. Reference Schematics2.7.2.1. Magnetics Integrated Into RJ-45 ReceptacleFigure 26: Magnetics Integrated Into RJ-45 Recep

COM Express Interfaces2.7.2.2. Discrete Coupling TransformerFigure 27: Discrete Coupling TransformerPICMG® COM Express® Carrier Board Design Guide Re

COM Express Interfaces2.7.3. Routing ConsiderationsThe 8-wire PHY / MDI circuit is required to meet a specific waveform template and associated signa

COM Express Interfaces2.8. USB PortsA COM Express Module must support a minimum of 4 USB Ports and can support up to 8 USB Ports. All of the USB Por

COM Express InterfacesTable 18: USB Signal DescriptionSignal Pin#Description I/O CommentUSB0+ A46 USB Port 0, data + or D+ I/O USB mandatory on Module

COM Express InterfacesThe first schematic is powered from VCC_5V_SBY Suspend power and can provide Wake on LAN support. The second schematic is power

COM Express InterfacesFigure 29: USB Reference DesignPICMG® COM Express® Carrier Board Design Guide Draft Rev. 2.0 / December 6, 2013 79/218USBP2J_EMI

Preface1. Preface1.1. About This DocumentThis document provides information for designing a custom system Carrier Board for COM Express Modules. It

COM Express Interfaces2.8.3. Avoiding Back-driving ProblemsFor more information please refer to chapter 2.9.3 'Avoiding Back-driving Problems&ap

COM Express Interfaces2.9. USB 3.0USB 3.0 is the third major revision of the Universal Serial Bus (USB) standard for computer connectivity. It adds

COM Express InterfacesSignal Pins T6 Pins T10 Description I/OUSB_SSRX3+ C13 USB Port 3, SuperSpeed RX + I PCIEUSB_SSRX3- C12 USB Port 3, SuperSpeed RX

COM Express Interfaces2.9.1.3. USB 3.0 connectorFigure 30: USB 3.0 ConnectorTable 23: USB 3.0 Connector Signal DescriptionSignal Pin Description I/O

COM Express Interfaces2.9.2. Reference Schematics2.9.2.1. USB 3.0 ExampleFigure 31: USB 3.0 Example SchematicJ5 incorporates a dual USB 3.0 Type A h

COM Express InterfacesESD protection diodes D7 through D12 provide overvoltage protection caused by ESD and electrical fast transients . Low capacita

COM Express Interfaces2.9.3. Avoiding Back-driving ProblemsFigure 32: Avoiding Back-drivingBack driving of power from a USB device to power rails on

COM Express Interfaces2.10. SATASupport for up to four SATA ports is defined on the COM Express A-B connector. Support for a minimum of two ports is

COM Express InterfacesTable 26: Serial ATA Power Connector Pin-outPins Signal Description1,2,3 +3.3V 3.3V power supply4,5,6 GND Ground7,8,9 +5V 5V pow

COM Express Interfaces2.10.2. Reference SchematicFigure 33: SATA Connector DiagramThe following notes apply to Figure 33 above.The Module provides a

Preface1.6. Name and logo usageThe PCI Industrial Computer Manufacturers Group’s policies regarding the use of its logos and trademarks are as follow

COM Express Interfaces2.10.3. Routing ConsiderationsRoute SATA signals as differential pairs, with a 85 Ω differential impedance and a 50 Ω, single-e

COM Express Interfaces2.11. LVDS2.11.1. Signal DefinitionsThe COM Express Specification provides an optional LVDS interface on the COM Express A-B c

COM Express Interfaces2.11.1.1. Connector and Cable ConsiderationsWhen implementing LVDS signal pairs on a single-ended Carrier Board connector, the

COM Express Interfaces2.11.1.4. Color Mapping and TermsFPD-Link and Open LDI Color MappingAn LVDS stream consists of frames that pack seven data bits

COM Express InterfacesTable 28: LVDS Display Terms and DefinitionsTerm DefinitionColor-MappingColor-mapping refers to the order in which display color

COM Express InterfacesThe Open LDI specification uses the term “pixel clock” differently from most other documents. In the Open LDI specification, th

COM Express InterfacesTable 30: LVDS Display: Dual Channel, Unbalanced Color-MappingXmit Bit OrderLVDSClockOpen LDI18 bit (36 bit)Dual ChOpen LDI24 bi

COM Express Interfaces2.11.2. Reference SchematicsFigure 34: LVDS Reference SchematicPICMG® COM Express® Carrier Board Design Guide Draft Rev. 2.0 /

COM Express Interfaces2.11.3. Routing ConsiderationsRoute LVDS signals as differential pairs (excluding the five single-ended support signals), with

COM Express Interfaces2.12. Embedded DisplayPort (eDP)Embedded DisplayPort (eDP) is a digital display interface standard produced by the Video Electr