
EDGE FINGER
(J3)
CPLD
(U20)
SITARA
CPU
(U7)
P62
P67
F3
G1
L5
K5
AE27
AF28
USB0_EN_OC#
USB1_OC#
USB0_OC#
USB1_EN_OC#
10K
USB1_EN_OC_PU
USB0_EN_OC_PU
K10
F1
10K
1v8 to 3v3
Translator
EN_USB0_VBUS_1V8
EN_USB1_VBUS_1V8
EN_USB0_VBUS_3V3
EN_USB1_VBUS_3V3
B1
C1
L5
AF11
3v3 to 1v8
Translator
USB0_OC_3V3#
USB1_OC_3V3#
Figure 4: External USB Port Power Distribution Logic Implementation
USB port power enable and over current logic implementation between the TI AM3874CPU and CPLD is shown in
the table below:
EN_USB0_VBUS_1V8/
EN_USB0_VBUS_3V3
EN_USB1_VBUS_1V8/
EN_USB1_VBUS_3V3
USB Port0 over current indication
signal
USB Port1 over current indication
signal
USB port power-enable and over-current logic implementation between the CPLD and ULP-COM sA3874i edge
connector is shown in the table below:
ULP-COM sA3874i
Edge Finger
USB Port0 power enable/over current
indication signal
USB Port1 power enable/over current
indication signal
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