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User’s Guide

3.2.18 SPI Interfaces

The ULP-COM sA3874i module supports two external SPI interfaces that are available off-Module for general

purpose use.

SPI interface signals are exposed on the ULP-COM sSA3874i edge connector as shown below:

ULP-COM sA3874i Edge finger

TI Cortex A8 CPU

Net Name

Notes

Pin #

Pin Name

Pin #

Pin Name

SPI0

P43

SPI0_CS0#

AC17

SPI[3]_SCS[0]n

SPI3_CS0#

SPI 0 Master Chip Select 0

output

P31

SPI0_CS1#

AG27

SPI[3]_SCS[1]n

SPI3_CS1#

SPI 0 Master Chip Select 1

output

P44

SPI0_CK

AE18

SPI[3]_SCLK

SPI3_CK

SPI 0 Master Clock output

P45

SPI0_DIN

AC16

SPI[3]_D[1]

SPI3_DIN

SPI 0 Master Data input

(input to CPU, output from

SPI device)

P46

SPI0_DO

AC21

SPI[3]_D[0]

SPI3_DO

SPI 0 Master Data output

(output from CPU, input to

SPI device)

SPI1

P54

SPI1_CS0#

AD3

SPI[1]_SCS[0]#

SPI1_CS0#

SPI 1 Master Chip Select 0

output

P55

SPI1_CS1#

SPI[1]_SCS[1]n

SPI1_CS1#

SPI 1 Master Chip Select 1

output

P56

SPI1_CK

AC3

SPI[1]_SCLK

SPI1_CK

SPI 1 Master Clock output

P57

SPI1_DIN

AA6

SPI[1]_D[0]

SPI1_DIN

SPI 1 Master Data input

(input to CPU, output from

SPI device)

P58

SPI1_DO

AA3

SPI[1]_D[1]

SPI1_DO

SPI 1 Master Data output

(output from CPU, input to

(SPI device)

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 79 80

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