
3.2.13 PCIe Interface
The ULP-COM sA3874i module supports one PCIe GEN2 interface. PCIe interface signals are exposed on the ULP-
COM sA8374 edge connector as shown below:
ULP-COM sA3874i Edge
Finger
Differential PCIe Link A transmit
data pair 0. Series decoupling
caps are provided in the Module.
Differential PCIe Link A receive
data pair 0. Series decoupling
caps are not provided in the
Module.
Differential PCIe Link A
reference clock output
PCIe Port A clock request input
PCIE_A_PRSNT#/PC
IE_A_PRSNT_1V8#
PCIe Port A present input
PCIe Port A reset output, active
low is generated from CPLD
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