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KTGM45 Users Guide

KTD-N0793-O Page 56

3.19.1 Signal Description – PCI Slot Connector

SYSTEM PINS

CLK

Clock provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals,

except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on the risingedge

of CLK and all other

timing parameters are defined with respect to this edge. PCI operates at 33MHz.

PME#

Power Management Event interrupt signal. Wake up signal.

RST#

Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. What effect

RST# has on a device beyond the PCI sequencer is beyond the scope of this specification, except for

reset states of required PCI configuration registers. Anytime RST# is asserted, all PCI output signals must

be driven to their benign state. In general, this means they must be asynchronously tri-stated. SERR#

(open drain) is floated. REQ# and GNT# must both be tri-

stated (they cannot be driven low or high during

reset). To prevent AD, C/BE#, and PAR signals from floating during

reset, the central resource may drive

these lines during reset (bus parking) but only to a logic low level–they may not be driven high.

RST# may be asynchronous to CLK when asserted or deasserted. Although asynchronous, deassertion is

guaranteed to be a clean, bounce-

free edge. Except for configuration accesses, only devices that are

required to boot the system will respond after reset.

ADDRESS AND DATA

AD[31::00]

Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase

followed by one or more data phases. PCI supports both read and write bursts.

The address phase is the clock cycle in which FRAME# is asserted. During the address phase AD[31::00]

contain a physical address (32 bits). For I/O, this is a byte address; for configuration and memory, it is a

DWORD address. During data phases AD[07::00] contain the least significant byte (lsb) and AD[31::24]

contain the most significant byte (msb). Write data is stable and valid when IRDY# is asserted and read

data

is stable and valid when TRDY# is asserted. Data is transferred during those clocks where both

IRDY# and TRDY# are asserted.

C/BE[3::0]#

Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a

transaction, C/BE[3:

:0]# define the bus command. During the data phase C/BE[3::0]# are used as Byte

Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry

meaningful data. C/BE[0]# applies to byte 0 (lsb) and C/BE[3]# applies to byte 3 (msb).

PAR

Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI agents.

PAR is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one

clock after either IRDY# is

asserted on a write transaction or TRDY# is asserted on a read transaction.

Once PAR is valid, it remains valid until one clock after the completion of the current data phase. (PAR

has the same timing as AD[31::00], but it is delayed by one clock.) The master drives PAR for address and

write data phases; the target drives PAR for read data phases.

INTERFACE CONTROL PINS

FRAME#

Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME#

is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue.

When FRAME# is deasserted, the transaction is in the final data phase or has completed.

IRDY#

Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of

the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock both

IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on

AD[31::00]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until

both IRDY# and TRDY# are asserted together.

TRDY#

Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of

the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock both

TRDY# and IRDY# are sampled

asserted. During a read, TRDY# indicates that valid data is present on

AD[31::00]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until

both IRDY# and TRDY# are asserted together.

STOP#

Stop indicates the current target is requesting the master to stop the current transaction.

LOCK#

Lock indicates an atomic operation that may require multiple transactions to complete. When LOCK# is

asserted, non-exclusive transactions may proceed to an address that is not curr

ently locked. A grant to

start a transaction on PCI does not guarantee control of LOCK#. Control of LOCK# is obtained under its

own protocol in conjunction with GNT#. It is possible for different agents to use PCI while a single master

retains ownership of

LOCK#. If a device implements Executable Memory, it should also implement LOCK#

and guarantee complete access exclusion in that memory. A target of an access that supports LOCK#

must provide exclusion to a minimum of 16 bytes (aligned). Host bridges that have system memory behind

them should implement LOCK# as a target from the PCI bus point of view and optionally as a master.

IDSEL

Initialization Device Select is used as a chip select during configuration read and write transactions.

DEVSEL#

Device Select, when actively driven, indicates the driving device has decoded its address as the target of

the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.

(Continues)

Connector Definitions

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